Sundance SMT365G Bedienungsanleitung

User Manual (QCF42); Version 3.0, 5/2/01; © Sundance Multiprocessor Technology Ltd. 2001 SMT365G User Manual

Version 1.0.0 Page 10 of 23 SMT365G User Manual ZBTRAM Memory space CE0 is used to access 8MB of ZBTRAM over EMIFA. The ZBTRAM operates at the exte

Version 1.0.0 Page 11 of 23 SMT365G User Manual Address Flash page selected 0x6C000000 Page 0 (1st and 3rd sections enabled) 0x6C000001 Page 1 (

Version 1.0.0 Page 12 of 23 SMT365G User Manual Reprogramming the firmware and boot code Please refer to the following documentation: http://www.su

Version 1.0.0 Page 13 of 23 SMT365G User Manual Interrupts See general firmware description [7] SDL/Communication ports The SMT365G provides 6 ComP

Version 1.0.0 Page 14 of 23 SMT365G User Manual Global bus The SMT365G provides one global bus interface. See general firmware description [7] LE

Version 1.0.0 Page 15 of 23 SMT365G User Manual FPGA space availability The firmware is generated with Xilinx ISE. Table below gives the device uti

Version 1.0.0 Page 16 of 23 SMT365G User Manual General Requirements The module must be fixed to a TIM40-compliant carrier board. The SMT365G TIM i

Version 1.0.0 Page 17 of 23 SMT365G User Manual Connector Positions

Version 1.0.0 Page 18 of 23 SMT365G User Manual Serial Ports & Other C60 I/O The C60 contains various I/O ports. These signals are connected to

Version 1.0.0 Page 19 of 23 SMT365G User Manual Virtex Memory Map See general firmware description. The memory mapping is as follows: #define SMT3

Version 1.0.0 Page 2 of 23 SMT365G User Manual Revision History Date Comments Engineer Version 23/09/04 First rev, based on 365 user manual (v1

Version 1.0.0 Page 20 of 23 SMT365G User Manual #define GLOBAL_BUS_START (volatile unsigned int *)0x90088000 #define GLOBAL_BUS_LENGTH (volat

Version 1.0.0 Page 21 of 23 SMT365G User Manual SHB pin-out Pin Signal Signal Pin 1 SDBA_CLK SDBA_DATA0 2 3 SDBA_DATA1 SDBA_DATA2 4 5 SDBA_DATA3

Version 1.0.0 Page 22 of 23 SMT365G User Manual Bibliography 1. TMS320C6201/C6701 Peripherals Reference Guide (literature number SPRU190) http:/

Version 1.0.0 Page 23 of 23 SMT365G User Manual Index Architecture Description...7 Bibliography...

Version 1.0.0 Page 3 of 23 SMT365G User Manual Table of Contents Revision History ...

Version 1.0.0 Page 4 of 23 SMT365G User Manual FPGA space availability ...

Version 1.0.0 Page 5 of 23 SMT365G User Manual The format of registers is described using diagrams of the following form: 31–24 23–16 15–8 7–0

Version 1.0.0 Page 6 of 23 SMT365G User Manual Outline Description The SMT365G is a C64xx-based size 1 TIM offering the following features:  TM

Version 1.0.0 Page 7 of 23 SMT365G User Manual Block Diagram Architecture Description The SMT365G TIM consists of a Texas Instruments TMS320C6

Version 1.0.0 Page 8 of 23 SMT365G User Manual TMS320C6416T The processor will run with zero wait states from internal SRAM. An on-board crystal o

Version 1.0.0 Page 9 of 23 SMT365G User Manual EMIF Control Registers The C6416T has two external memory interfaces (EMIFs). One of these is 64 bi