Sundance SMT391-VP Bedienungsanleitung

SMT391-VP User Manual

Version 1.3 Page 10 of 41 SMT391-VP User Manual SLB The SMT391-VP is composed of the SMT391 module plugged on the base module SMT338-VP. Both modu

Version 1.3 Page 11 of 41 SMT391-VP User Manual Clocks generation The sampling clock of the ADC can be generated by an on-board VCO or an on-board

Version 1.3 Page 12 of 41 SMT391-VP User Manual - CLKI Æ ADCQ Any other configuration isn’t supported by the SMT391-VP. For example the interlaci

Version 1.3 Page 13 of 41 SMT391-VP User Manual When the SMT391-VP receives a trigger, the SMT391 interface block gets activated and starts capturi

Version 1.3 Page 14 of 41 SMT391-VP User Manual Registers block This block implements the registers of the SMT391-VP. The complete description of

Version 1.3 Page 15 of 41 SMT391-VP User Manual Number of RAMB16s 14 out of 136 10% Number of SLICEs 4

Version 1.3 Page 16 of 41 SMT391-VP User Manual Software An example is provided to get started with the SMT391-VP. The example configures the mod

Version 1.3 Page 17 of 41 SMT391-VP User Manual SMT391_Adc_Init() SMT391_Adc_Init configure the ADC’s internal registers. Prototype void SMT391_Adc

Version 1.3 Page 18 of 41 SMT391-VP User Manual Rf_Frequency: the frequency of the RF part of the PLL. This is the sampling frequency of the ADC.

Version 1.3 Page 19 of 41 SMT391-VP User Manual Description of the registers The registers in the SMT391-VP firmware control the complete functiona

Version 1.3 Page 2 of 41 SMT391-VP User Manual Revision History Date Comments Engineer Version 25/04/05 First release JPA 1.0 07/06/05 Added:

Version 1.3 Page 20 of 41 SMT391-VP User Manual 0xF Reserved Figure 4 – Packet Structure – Defined Commands. Example 1: Sending 0x1001FFFF over C

Version 1.3 Page 21 of 41 SMT391-VP User Manual Memory map The write packets must contain the address where the data must be written to and the rea

Version 1.3 Page 22 of 41 SMT391-VP User Manual 0x022 Reserved 0x022 Smt338SerialNoA 0x023 Reserved 0x023 Smt338SerialNoB 0x024 Reserved 0x

Version 1.3 Page 23 of 41 SMT391-VP User Manual 0x805 Smt391Pll_IfN_Reg2 0x805 Reserved 0x806 Smt391Pll_RfR_Reg1 0x806 Reserved 0x807 Smt391

Version 1.3 Page 24 of 41 SMT391-VP User Manual Bit 4: SDB B reset. Bit 5: RSL A reset. Bit 6: RSL B reset. Bit 7: Trigger logic reset channel Q (d

Version 1.3 Page 25 of 41 SMT391-VP User Manual (2) – SMT338-VP FPGA temperature on Bottom of PCB (3) – SMT391 Air Temperature on Bottom of PCB (

Version 1.3 Page 26 of 41 SMT391-VP User Manual 0x2 0x2 0x2 0x2 0x022 0x023 0x024 0x025 SMT338-VP Serial No SMT338-VP Serial No SMT338-VP Serial No

Version 1.3 Page 27 of 41 SMT391-VP User Manual Command Address Data MSB Data LSB 0x1 0x800 Data Data Figure 13 – Clock Synthesizer Setup Reg

Version 1.3 Page 28 of 41 SMT391-VP User Manual Smt391Pll_IfR_Reg2 - Smt391Pll_RfR_Reg2 Byte Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 B

Version 1.3 Page 29 of 41 SMT391-VP User Manual ADC Setup Registers (Write Add 0x80B, 0x80C) These registers configure the internal functionality o

Version 1.3 Page 3 of 41 SMT391-VP User Manual Table of Contents Revision History...

Version 1.3 Page 30 of 41 SMT391-VP User Manual Installation How to connect your SMT391 to your SMT338-VP? The following diagram shows both the SMT

Version 1.3 Page 31 of 41 SMT391-VP User Manual Figure 17 – Components Used to Connect the SMT391 to the SMT338-VP. 1) First fit two Nylon scre

Version 1.3 Page 32 of 41 SMT391-VP User Manual Figure 18 – Fitting of Nylon Screws and Nuts to the SMT338-VP. Figure 19 – Securing the SMT338

Version 1.3 Page 33 of 41 SMT391-VP User Manual Figure 20 – Connecting the SMT391 to the SMT338-VP Configuring the FPGA A microcontroller MSP430

Version 1.3 Page 34 of 41 SMT391-VP User Manual First off the LE line is pulled low and then the MSB of data is loaded onto the Data line. The Clo

Version 1.3 Page 35 of 41 SMT391-VP User Manual Figure 23 – State Machine Driving the PLL Serial Interface. Clock synthesiser interface A three w

Version 1.3 Page 36 of 41 SMT391-VP User Manual The Clock Synthesizer register (present on the SMT338-VP firmware side) is used for the setup of th

Version 1.3 Page 37 of 41 SMT391-VP User Manual Figure 26 – Clock Synthesizer Division Setup. The M count bits are used to configure the clock ou

Version 1.3 Page 38 of 41 SMT391-VP User Manual Figure 28 – Timing Diagram for the Atmel ADC. Sdata gets clocked into the ADC on the rising edges

Version 1.3 Page 39 of 41 SMT391-VP User Manual The state machine waits for the AdcFlag to go high before it switches to the Initialize state. In t

Version 1.3 Page 4 of 41 SMT391-VP User Manual RSL...

Version 1.3 Page 40 of 41 SMT391-VP User Manual Physical Properties Dimensions Weight Supply Voltages Supply Current +12V +5V +3.

Version 1.3 Page 41 of 41 SMT391-VP User Manual The following table lists the internal SMT391 voltages that are derived from the voltages that are

Version 1.3 Page 5 of 41 SMT391-VP User Manual Physical Properties...

Version 1.3 Page 6 of 41 SMT391-VP User Manual Introduction Overview The SMT391-VP is a single width TIM module. It is capable of sampling two anal

Version 1.3 Page 7 of 41 SMT391-VP User Manual Related Documents [1] Sundance High-speed Bus (SHB) specifications – Sundance. ftp://ftp2.sundance.

Version 1.3 Page 8 of 41 SMT391-VP User Manual Hardware overview Block diagram The following diagram represents the architecture of the SMT391-VP m

Version 1.3 Page 9 of 41 SMT391-VP User Manual The SMT391-VP is made of two sub-modules combined. To make a SMT391-VP you combine the base module